The present invention relates to a nonvolatile magnetic memory device and a manufacturing method thereof. More specifically, the present invention relates to a nonvolatile magnetic memory device called a TMR (Tunnel Magnetoresistance) type MRAM (Magnetic Random Access Memory) and a manufacturing method thereof.
With great diffusion of information communication machines, particularly, personal small machines such as personal digital assistances, various semiconductor devices such as a memory, a logic and so on, constituting such machines are being demanded to cope with higher performances such as a higher degree of integration, faster operation capability and lower power consumption. Particularly, a nonvolatile memory is considered indispensable in the ubiquitous era. Even if the depletion of a power supply or some troubles occur or a server is disconnected to a network due to some failure, important information can be stored or protected with a nonvolatile memory. Further, recently available personal digital assistances are designed such that the power consumption is reduced to a lowest level possible by maintaining non-operating circuit blocks in a standby state, and the waste of power consumption and a memory can be avoided if a nonvolatile memory capable of working as a fast-speed work memory and a mass-storage memory can be realized. Further, if a fast-speed and mass-storage nonvolatile memory can be realized, the “instant-on” function of booting in the instance of turning on power can be made possible.
The nonvolatile memory includes a flash memory using a semiconductor material and a ferroelectric nonvolatile semiconductor memory (FERAM, Ferroelectric Random Access Memory) using a ferroelectric material. However, the flash memory has a defect that the writing speed is slow since it is in the order of microseconds. On the other hand, in FERAM, the number of times of re-writability thereof is 1012 to 1014, and the number cannot be said to be sufficient for replacing SRAM or DRAM with FERAM, and there is pointed out another problem that the micro-fabrication of a ferroelectric layer is difficult.
As a nonvolatile memory free of the above defects, a nonvolatile memory device called MRAM (Magnetic Random Access Memory) is in the limelight. The MRAM at an early development stage was based on a spin valve using a GMR (Giant magnetoresistance) effect. Since, however, the memory cell resistance against a load is as low as 10 to 100 Ω, the power consumption per bit on readout is large, and the defect is that it is difficult to attain the capacity of mass storage.
While the MRAM using a TMR (Tunnel Magnetoresistance) effect had a resistance change ratio of 1–2% at room temperature at an early development stage, it has come to be possible to obtain a resistance change ratio close to 20% in recent years, so that the MRAM using the TMR effect is highlighted. The TMR-type MRAM has a simple structure and enables easy scaling, and recording is made by the rotation of a magnetic moment, so that the number of times of possible re-writing is great. Further, it is expected that the TMR-type MRAM is very rapid with regard to an access time period, and it is already said that the TMR-type MRAM is capable of an operation at 100 MHz.
FIG. 34 shows a schematic partial cross-sectional view of a conventional TMR-type MRAM (to be simply referred to as “MRAM” hereinafter). The MRAM comprises a transistor for selection TR made of a MOS-type FET and a tunnel magnetoresistance device 130.
The tunnel magnetoresistance device 130 has a stacking structure composed of a first ferromagnetic layer, a tunnel barrier 133 and a second ferromagnetic layer. More specifically, the first ferromagnetic layer has a two-layer structure, for example, of an anti-ferromagnetic layer 131 positioned below and a ferromagnetic layer (called a reference layer or pinned magnetic layer 132 as well) positioned above and has an intense unidirectional magnetic anisotropy due to an exchange interaction working between these two layers. The second ferromagnetic layer of which the magnetization direction rotates relatively easily is also called a free layer or memory layer 134. The tunnel barrier 133 works to cut a magnetic coupling between the memory layer 134 and the pinned magnetic layer 132 and also to flow a tunnel current. A bit line BL for connecting the MRAMs is formed on an insulating interlayer 126. A top coating film 135 formed between the bit line BL and the memory layer 134 works to prevent mutual diffusion of atoms constituting the bit line BL and atoms constituting the memory layer 134, to reduce a contact resistance and to prevent the oxidation of the memory layer 134. In Figure, reference numeral 136 indicates a lead electrode connected to a lower surface of the anti-ferromagnetic layer 131.
Further, a write-in word line RWL is arranged below the tunnel magnetoresistance device 130 through an insulating interlayer 124. Generally, the extending direction (first direction) of the write-in word line RWL and the extending direction (second direction) of the bit line BL cross each other at right angles.
The transistor for selection TR is formed in that portion of a semiconductor substrate 110 which portion is surrounded by a device isolation region 111, and the transistor for selection TR is covered with an insulating interlayer 121. One source/drain region 114B is connected to the lead electrode 136 of the tunnel magnetoresistance device 130 through a tungsten plug 122, a landing pad 123 and a tungsten plug 125. The other source/drain region 114A is connected to a sense line 116 through a tungsten plug 115. In Figure, reference numeral 112 indicates a gate electrode, and reference numeral 113 indicates a gate insulating film.
In an MRAM array, the MRAM is arranged in an intersecting point of the bit line BL and the write-in word line RWL.
When data is written into the above-constituted MRAM, current is flowed in the bit line BL and the write-in word line RWL, to form a synthetic magnetic field, and the direction of magnetization of the second ferromagnetic layer (memory layer 134) is changed by means of the synthetic magnetic field, whereby, “1” or “0” is recorded into the second ferromagnetic layer (memory layer 134).
Data is read out by bringing the transistor for selection TR into an ON-state, flowing a current in the bit line BL and detecting a tunnel current change caused by a magnetoresistance effect with the sense line 116. When the magnetization direction of the memory layer 134 and the counterpart of the pinned magnetic layer 132 are the same, a low-resistance state results (this state represents, for example, “0”), and when the magnetization direction of the memory layer 134 and the counterpart of the pinned magnetic layer 132 are antiparallel, a high-resistance state results (this state represents, for example, “1”).
FIG. 35 shows an asteroid curve of the MRAM. A current is flowed in the bit line BL and the write-in word line RWL, and as a result, a synthetic magnetic field is generated. Data is written into the tunnel magnetoresistance device 130 constituting the MRAM on the basis of the synthetic magnetic field. A magnetic field (HEA) in the easy-magnetization axis direction of the memory layer 134 is formed due to a writing current flowing in the bit line BL, and a magnetic field (HHA) in the difficult-magnetization axis direction of the memory layer 134 is formed due to a current flowing the write-in word line RWL. In some MRAM constitution, a magnetic field (HHA) in the difficult-magnetization axis direction of the memory layer 134 is formed due to a writing current flowing in the bit line BL, and a magnetic field (HEA) in the easy-magnetization axis direction of the memory layer 134 is formed due to a current flowing the write-in word line RWL.
The asteroid curve shows an inversion threshold value of magnetization direction of the memory layer 134 due to the synthetic magnetic field (synthesis of magnetic field vectors of the magnetic field HHA and the magnetic field HEA to be exerted on the memory layer 134). When a synthetic magnetic field corresponding to an outside (OUT1, OUT2) of the asteroid curve is generated, the magnetization direction of the memory layer 134 is inverted, so that writing of data is performed. When a synthetic magnetic field corresponding to an inside (IN) of the asteroid curve is generated, the inversion of magnetization of the memory layer 134 does not take place. Further, in the MRAM other than the MRAM which is positioned in the intersecting point of the write-in word line RWL and the bit line BL in which the current is flowing, a magnetic field is additionally generated by the write-in word line RWL or bit line BL alone, and when such a magnetic field is greater than a unidirectional inversion magnetic field HK [in a region (OUT2) outside dotted lines in FIG. 35], the magnetization direction of the memory layer 134 constituting the MRAM other than the MRAM which is positioned in the intersecting point is also inverted. Therefore, only when the synthetic magnetic field is outside the asteroid curve and is in a region (OUT1) inside the dotted lines in FIG. 35, selective writing into the selected MRAM is possible.
The TMR-type MRAM has advantages that it is easy to attain higher speed and higher degree of integration as described above, while it has a defect that the current consumption for writing is greater than that in any other memory device. Writing data into the TMR-type MRAM is performed by a synthetic magnetic field formed by a current flowing the bit line BL and a current flowing the write-in word line RWL. The magnetic field for inverting the magnetization direction of the memory layer 134 is approximately 20 to 200 oersteds (Oe), and the current required for the inversion amounts to several milliamperes to several tens milliamperes. Such a large current value is a big problem when the TMR-type MRAM is used in a personal small item. Further, since a driver for large-current driving is required, the area occupied by such a driver is large, which can inhibit the attaining of a higher integration degree.
From the viewpoint of a higher integration degree, the line width of the bit line and the write-in word line is required to be a line width close to a minimum line width determined depending upon lithography technology. When the bit line BL and the write-in word line RWL (these will be sometimes generally referred to as “wiring” hereinafter) are supposed to have a line width of 0.3 μm and a thickness of 0.5 μm, a current flowing in the wiring comes to have a current density of 6×106 A/cm2, and even when copper (service current density: 0.5×106 A/cm2 to 1×106 A/cm2) is used as a material for constituting the wiring, there is caused a crucial problem that the service life and the reliability of the wiring is decreased due to electromigration. Further, as the MRAM is gradually minimized in size, it is required to reduce the dimensions of the wiring, so that the reliability problem of the wiring becomes more crucial.
Moreover, due to minimizing of the MRAM in size, a magnetic field is exerted on an adjacent MRAM due to the leak of a magnetic flux, so that there is caused a disturbance problem.
In an MRAM disclosed in U.S. Pat. No. 5,940,319, a wiring positioned above and/or below a tunnel magnetoresistance device has a portion that does not face the tunnel magnetoresistance device and which is covered with a material for concentrating magnetic fluxes. FIG. 36 shows a schematic partial cross-sectional view of the MRAM disclosed in the above U.S. Pat. In the MRAM shown in FIG. 36, a magnetic flux concentration structure is applied to a write-in word line RWL. That is, side surfaces and a lower surface of the write-in word line RWL are covered with a high magnetic permeability material 140, whereby the effect of concentrating magnetic fluxes on the memory layer 134 is enhanced.
FIGS. 37 and 38 show simulation results of magnetic flux distributions in the vicinity of tunnel magnetoresistance devices in the conventional MRAMs having structures shown in FIGS. 34 and 36. In FIGS. 37 and 38, the tunnel magnetoresistance devices are indicated by TMR.
One of causes for preventing the attaining of a higher integration degree of the MRAM is that the write-in word line RWL is formed below the tunnel magnetoresistance device 130 through the insulating interlayer 124. That is, for attaining a high integration degree of the MRAM, in other words, for materializing a minimum cell size, it is said that the width of the tunnel magnetoresistance device 130 is required to be equal to, or smaller than, the width of the write-in word line RWL. Generally, however, a mask alignment deviation exists between the lithography step for forming the write-in word line RWL and the lithography step for forming the tunnel magnetoresistance device 130, so that it is difficult to materialize the minimum cell size.
In the MRAM disclosed in U.S. Pat. No. 5,940,319, there is produced an effect of enhancing the concentration of magnetic fluxes on the memory layer 134. However, the write-in word line RWL and the memory layer 134 are away from each other, so that the effect of concentrating the magnetic fluxes is not sufficient. As a result, there is involved a problem that the current consumption is not fully decreased. Further, since the write-in word line RWL and the tunnel magnetoresistance device 130 are formed in different mask steps as described above, not only it is difficult to materialize the minimum cell size, but also there is a problem that when a mask alignment deviation takes place, the asteroid curve comes to be asymmetric, which results in large fluctuation in writing characteristics.